1. Field of the Invention
The present invention is related to dual- or multi-port memories and, in particular, to bit-line layouts within such memory arrays.
2. Background of the Invention
One problem with dual and multi port memories is the capacitance that occurs between or as a result of the bit lines. For example, current dual or multi port memory devices have long bit lines that produce greater amounts of stray and cross coupling capacitances between the bit lines. Such increased capacitance can produce increased delay times related to access to the memory system and otherwise impact device speed and performance. Additionally, executing of simultaneous read and write operations in a cell in the same column can further exaggerate these capacitance problems. Moreover, capacitively induced cross-talk can occur between bit lines. In sum, all of these factors can significantly decrease the performance of the memory system.
Accordingly, there is a need for dual port memory systems that reduce or minimize the capacitive coupling between and other capacitance associated with bit lines.